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OKI Semiconductor ML2500BTA
GENERAL DESCRIPTION
FEDL2500BFULL-02
Issue Date: Aug.9, 2004
Analog-Storage Single-chip Record/Playback LSI with 1M Bit-Cell Flash Memory
Thanks to newly developed Analog Multi-Level Storage technology, ML2500B stores non-compressed analog source signal directly into on-chip 1M Bit-Cell Flash memory. The result is superb sound quality without noise and distortions introduced through coding/decoding, and impressive long-time record/playback capability up to 256 sec. ML2500B is fully controllable by an external MCU via the industry's standard Serial Peripheral Interface. In addition, no backup requirement and low operating voltage (2.7 to 3.3 V) make the LSI an ideal choice for compact, handy and portable terminals. ML2500B is a true single-chip solution to record/playback subsystem for use with today's size-critical electronic products.
DIFFERENCES BETWEEN THE ML2500BTA AND THE ML2500TA
ML2500BTA Operating Temperature Pin Symbol AC Characteristic Ta = -40 to +70C Pin 10: TEST2 DI hold time tDIH = 30 ns ML2500TA Ta = -10 to +70C Pin 10: NC DI hold time tDIH = 20 ns
FEATURES
*On-chip non-volatile 1M bit-cell Flash memory Program/Erase Cycles: 10,000 cycles Data Retention : 10 years *MCU Interface Serial Peripheral Interface (SPI; Mode 0) *Record/Playback Time Length (With the int. Osc. or ext. clock at 8.192 MHz) Approx. 160 sec (At fsam = 6.4 kHz) Approx. 190 sec (At fsam = 5.3 kHz) Approx. 256 sec (At fsam = 4.0 kHz) *Selectable Sampling Frequencies 4.0 kHz, 5.3 kHz, 6.4 kHz *Maximum number of recording phrases: 320 phrases *Phrase Control Fully controllable with user-definable Start, Stop addresses *Built-in LPF/Smoothing Filter (LPF attenuation -40 dB/oct) *Built-in Oscillation Circuit (8.192 MHz), No oscillator required Optional external clock input (Clock Frequency 4.0 to 8.192 MHz) *Power Supply : 2.7 to 3.3 V *Operating Temperature: -40 to +70C (guaranteed for both function and voice quality) -40 to +85C (guaranteed for function only) *Notice *Notice The voice quality can deteriorate at temperatures beyond the range of -40 to +70C. DC and AC characteristics in this data sheet are specified for -40 to +70C operating temperature range. *Package: 32-pin Plastic TSOP (TSOP(1)32-P-814-0.50-1K) (Product name: ML2500BTA) Note: Please contact the Oki Sales office/Distributors for bare chips.
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CONTENTS
GENERAL DESCRIPTION ................................................................................................................................... 1 FEATURES ............................................................................................................................................................ 1 BLOCK DIAGRAM ............................................................................................................................................... 3 PIN CONFIGURATION ........................................................................................................................................ 3 PIN DESCRIPTIONS ............................................................................................................................................. 4 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 5 RECOMMENDED OPERATING CONDITIONS................................................................................................. 5 ELECTRICAL CHARACTERISTICS ................................................................................................................... 5 DC Characteristics............................................................................................................................................. 5 Analog Characteristics ...................................................................................................................................... 6 AC Characteristics 1.......................................................................................................................................... 7 AC Characteristics 2.......................................................................................................................................... 8 TIMING DIAGRAM .............................................................................................................................................. 8 Serial Peripheral Interface (SPI) AC Characteristics Timing Chart .................................................................. 8 Operational Timing at Power-On ...................................................................................................................... 9 Timing for Power Up and Power Down Operations.......................................................................................... 9 Timing for Record/Playback Operation .......................................................................................................... 10 1. Timing for Recording Operation.......................................................................................................... 10 2. Timing for Playback Operation............................................................................................................ 11 3. Timing for Pausing Operation by the PAUSE Command.................................................................... 12 FUNCTIONAL DESCRIPTION .......................................................................................................................... 14 Serial Peripheral Interface (SPI)...................................................................................................................... 14 1. Timing for Writing Command Data..................................................................................................... 14 2. Timings for Reading out Status Data ................................................................................................... 15 Control Commands.......................................................................................................................................... 16 1. Control Commands-Recording ............................................................................................................ 16 2. Control Commands-Playback .............................................................................................................. 18 3. The List of Control Commands............................................................................................................ 19 Addressable Memory Space for Recording..................................................................................................... 20 Address Control............................................................................................................................................... 21 1. Address Control for Recording ............................................................................................................ 21 2. Address Control for Playback .............................................................................................................. 21 LPF Cheracteristics ......................................................................................................................................... 22 Power Supply Circuit Design .......................................................................................................................... 22 LOUT Output Voltage Range Allowance ....................................................................................................... 23 States of Output Pins during Power Down...................................................................................................... 23 APPLICATION CIRCUITS ................................................................................................................................. 24 PACKAGE DIMENSIONS .................................................................................................................................. 25
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BLOCK DIAGRAM
LOUT
LIN
- +
LPF
+ -
AOUT
SG
SG
Analog Write & Read Circuits 1M Bit Cell Analog Storage Flash Memory Array Address Decoder AVDD AGND TEST1 TEST2
ROSC
Internal Oscillator
EXTCLK
MUX
Serial Peripheral Interface & Controller
Power Supplies
RESET CS
SCK
DI
DO
MON
DVDD DGND
PIN CONFIGURATION (TOP VIEW)
DVDD 1 RESET 2 CS 3 SCK 4 DI 5 DO 6 MON 7 EXTCLK 8 NC 9 TEST2 10 TEST2 11 NC 12 TEST2 13 NC 14 ROSC 15 DGND 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
AVDD LIN LOUT TEST2 TEST2 AOUT SG NC TEST1 NC TEST2 NC TEST2 NC TEST2 AGND
NC: No connection. Keep NC pins open. 32-Pin Plastic TSOP (Type 1)
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PIN DESCRIPTIONS
Pin 5 6 4 3 2 Symbol Dl DO SCK CS RESET Type l O l l l Description Serial input pin for command data. Serial output pin for status data. Shift clock input pin for the Dl and the DO pins. Chip select pin. "L" level input enables data input/output through the serial interface. RESET input pin, resetting the serial interface circuit only. "L" level input to this pin initializes the serial interface. Must input "L" pulse after each power-on. Insert a 30 k resistor (Precision within 1%) between this pin and the DGND pin. The same resistor should also be inserted if an external clock is used. The resistor value determines the frequency of the clock for control in this device. External clock input pin. Allowable clock frequency range is 4.0 to 8.192 MHz. When external clock is unused and internal oscillation clock is used, connect this pin to the DGND. Output "H" level during recording/playback operation. Analog reference voltage (Signal Ground Voltage) output pin. It is recommendable to insert a capacitor of 3300 pF or less between this pin and the AGND pin. Loads except for capacitors should not be connected to this pin. Inverting input pin for the internal OP amplifier. Non-inverting input pin is internally connected to SG voltage. Output pin from the internal OP amplifier. Analog waveform output. Connect to an amplifier to drive a SP. Pins for testing the LSl. Must be held "OPEN". LSl's testing pin. Must be connected to DGND. Digital power supply pin. Insert a 0.1 F or larger by-pass capacitor between this pin and the DGND pin. Digital Ground pin Analog power supply pin. Insert a 0.1 F or larger by-pass capacitor between this pin and the AGND pin. Analog Ground pin
15
ROSC
l
8 7 26
EXTCLK MON SG
l O O
31 30 27 10, 11, 13, 18, 20, 22, 28, 29 24 1 16 32 17
LIN LOUT AOUT TEST2 TEST1 DVDD DGND AVDD AGND
l O O O l -- -- -- --
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TSTG Condition Ta = 25C -- Rating -0.3 to +5.0 -0.3 to VDD+0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature External Clock Frequency 1 External Clock Frequency 2 *1 *1 Symbol VDD Top fEXTCLK1 fEXTCLK2 Condition DGND = AGND = 0 V -- Min. -- -- 3.85 7.70 Range 2.7 to 3.3 -40 to +70 Typ. 4.096 8.192 Max. 4.34 8.68 MHz MHz Unit V C
*1: Applicable only with external clock
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage "H" Output Voltage "L" Output Voltage "H" Input Current "L" Input Current *1 *1 *2 *2 *1 *1 DVDD = AVDD = 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = -40 to +70C Symbol Condition Min. Typ. Max. Unit VIH VIL VOH VOL IIH IIL IDD1 IDD2 IDD3 IDDS DGND = AGND = 0 V -- lOH = -40 A lOL = 2 mA VIH = VDD VIL = 0 V In Recording Operation In Playback Operation In Command-Wait State -- 0.8 x VDD -- VDD-0.3 -- -- -10 -- -- -- -- -- -- -- -- -- -- 30 20 5 -- -- 0.2 x VDD -- 0.45 10 -- 45 30 10 10 V V V V A A mA mA mA A
Operating Current Consumption 1 Operating Current Consumption 2 Operating Current Consumption 3 Powerdown Current Consumption
*1: Applied to logic input pins (DI, SCK, CS, RESET and EXTCLK) except ROSC and TEST1 pins. *2: Applied to logic output pins (DO and MON) except TEST2 pin.
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Analog Characteristics
Parameter LIN Input Impedance LOUT Load Resistance AOUT Load Resistance LOUT Output Voltage Allowance *5 *1 *3 *4 Voice voltage Beep voltage Input OP. Amplifier Open Loop Gain *2 DVDD = AVDD = 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = -40 to +70C Symbol Condition Min. Typ. Max. Unit RLIN GOP RLOUT RAOUT VLOUT -- fIN = 0 to 4 kHz -- -- -- With respect to SG voltage 1 40 200 50 0.5 -0.5 -- -- -- -- -- -- -- -- -- -- 2.2 +0.5 M dB k k V V
*1: *2: *3: *4: *5:
Applied to LIN pin. Applied to LIN and LOUT pins. Applied to LOUT pin. Applied to AOUT pin. Refer to "LOUT Output Voltage Range Allowance" section.
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AC Characteristics 1
Parameter External Clock Duty Cycle RESET Pulse Width Powering up time Power-down Shift Time after PDWN Command Input Power-down Shift Time after "L" Input to RESET pin CS "L" Level Pulse Width for Power-down Reset MON Rising Time after REC Command Input *1 DVDD = AVDD = 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = -40 to +70C Symbol Condition Min. Typ. Max. Unit fduty tRST tPWUP tPDWN tPDWNR tCSWL tRECM tRECR tPLYM tPLYR -- -- -- -- -- -- At fsam = 6.4 kHz -- -- -- At fsam = 4.0 kHz At REC At PLAY RPM Falling Time after STOP Command Input At REC At PLAY *1 *1 tSPCM tSPCM tSPCR tSPCR tPSCP tSPCP1 tSPCP2 fsam1 fsam2 fsam3 At fsam = 5.3 kHz At fsam = 6.4 kHz At fsam = 6.4 kHz At fsam = 4.0 kHz At fsam = 5.3 kHz At fsam = 6.4 kHz At fsam = 6.4 kHz At fsam = 6.4 kHz At fsam = 6.4 kHz At fsam = 6.4 kHz Ta = 25C, DVDD = AVDD = 3.0 V Ta = 25C, DVDD = AVDD = 2.7 to 3.0 V Ta = -40 to +70C 40 1 -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -3.0 -6.0 -3.0 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Defined Frequency Defined Frequency Defined Frequency +fsam2 60 -- 1 100 100 -- 165 220 11 11 305 280 266 165 305 280 266 165 165 165 165 +3.0 +6.0 +3.0 % s s s s ms s ms % s ms s s s s ms ms ms
RPM Rising Time after REC Command Input MON Rising Time after PLAY Command Input RPM Rising Time after PLAY Command Input MON Falling Time after STOP Command Input
VPM Bit Rising Time after PAUSE Command Input *1 VPM Bit Reset Time after PAUSE Command Input, while Pausing VPM Bit Reset Time after STOP Command Input, while Pausing *1 *1
Absolute Error Sampling Frequency VDD Variation Error When internal Error oscillation clock is used *2 Temperature Variation Error
*1: The value changes in proportion to the sampling frequency selected. *2: When a 30 k resistor is used between ROSC and DGND pins.
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AC Characteristics 2
Parameter CS - SCK Setup Time SCK - CS Hold Time SCK "H" Level Pulse Width SCK "L" Level Pulse Width Dl Setup Time Dl Hold Time DO Output Delay Time DO Output Enable Shift Time DO Output Hi-Z Shift Time Command Interval Time DVDD = AVDD = 2.7 to 3.3 V, DGND = AGND = 0 V, Ta = -40 to +70C Symbol Condition Min. Typ. Max. Unit tCSS tCSH tWH tWL tDIS tDIH tDOD tDOE tDOZ tCS -- -- -- -- -- -- -- -- -- -- 100 100 100 100 20 30 -- -- -- 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 150 150 -- ns ns ns ns ns ns ns ns ns s
TIMING DIAGRAM
Serial Peripheral Interface (SPI) AC Characteristics Timing Chart
tCSS tCS
CS(I) tWH SCK(I) tDIS DI(I) tDOD DO(O) Hi-Z tDOE tDOZ Hi-Z tDIH tWL tCSH
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Operational Timing at Power-On To initialize the internal serial interface circuit of ML2500B after power-on, you must input "L" pulse to the RESET pin at the timing shown below. After this "L" pulse input, the ML2500B enters into standby state (Command-wait state). Timing for inputting RESET pulse at Power-on
VDD 2.7 V tRST 1 s RESET(I)
PDWN command input
tPWUP 1 ms
CS
Status
Resetting
Powering Up
Standby (Command-wait)
Power Down
Timing for Power Up and Power Down Operations ML2500B stops its oscillation circuit to shift to power-down state either by using the PDWN command or by inputting Low level to the RESET pin. In power-down state, the ML2500B turns into low power consumption mode. Two options are available to power up the LSI again after power down by the PDWN command: 1. Input "L" pulse to the RESET pin, or 2. Input Low level to the CS pin. The following charts show timings for power up and power down operations. Timing for power-down operation by using the PDWN command
PDWN command input CS(I) tCSWL 1 s RESET(I) tPDWN 100 s Status Command-wait Power Down tRST 1 s tPWUP 1 ms Powering Up Command-wait Power up with RESET pin Power up with CS pin
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Timing for Power-down operation with RESET pin
Power-down with RESET pin RESET(I) tPDWNR 100 s Status Command-wait Power Down tPWUP 1 ms Powering Up Command-wait Power-up with RESET pin
Timing for Record/Playback Operation 1. Timing for Recording Operation The following chart shows timing for recording operation at 6.4 kHz sampling frequency. It is assumed that the Start and Stop Addresses are set by the STADR and SPADR commands prior to the REC command input.
Power-up CS(I) tRECM MON(O) RPM Bit(O) 62.5 ms(Typ.) 10 ms(Typ.) Status Power-down
Command-wait Erasing
REC command input
STOP command input tSPCM PDWN command input tSPCR
tRECR
tPDWN 200 ms(Typ.)
Command-wait Power-down
200 ms(Typ.)
Recording
Dummy Recording
(Note 1) It takes about 210 ms (Typ.) for the LSI to start actual recording after the REC command input, as the LSI first erase 1 sector before it can start recording. (Note 2) When recording is stopped by the STOP command, the LSI continues to record until the last address of the current page is reached. This "lag" recording time is the STOP command of about 62.5 ms (Typ.). Afterwards, dummy recording is taken place up to the end of the following sector (max. 2 sectors). This dummy recording takes about 200 ms (Typ.). The dummy recording is given in the device specification and the recording contents are undefined. (Note 3) It is recommended to use the power-down mode in order to reduce power consumption when record or playback are not performed.
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2. Timing for Playback Operation The following chart shows timing for playback operation at 6.4 kHz sampling frequency. It is assumed that the Start and Stop Addresses are set by the STADR and SPADR commands prior to the PLAY command input.
PDWN command input Power-up CS(I) tPLYM MON(O) tPLYR10 ms(Typ.) RPM Bit(O) AOUT(O) STOP command input PLAY command input tSPCM 165 s 165 s
tSPCR
tPDWN
Status
Power-down
Command-wait
Playing Back
Power-down
Command-wait
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3. Timing for Pausing Operation by the PAUSE Command The following charts show timings for pausing recording operation by using the PAUSE command at 6.4 kHz sampling frequency.
PAUSE command input CS(I) MON(O) RPM Bit(O) VPM Bit(O) PAUSE command input
tPSCP
tSPCP1
Status
Recording
Pausing
Recording
PAUSE command input CS(I)
STOP command input tSPCM
MON(O) RPM Bit(O) VPM Bit(O)
tSPCR tPSCP
tSPCP2
200 ms (Typ.) 62.5 ms (Typ.) Status Recording Pausing Recording Command Wait Dummy Recording
(NOTE) If the STOP command is input while recording is suspended by the PAUSE command, the LSI resumes recording and keeps on recording until the last address of the current page is reached. This "lag" recording time is about 62.5 ms (Typ.). Afterwards, dummy recording is taken place up to the end of the following sector (max. 2 sectors). This dummy recording takes about 200 ms (Typ.). The dummy recording is given in the device specification and the recording contents are undefined.
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The following charts show timings for pausing playback by using the PAUSE command at 6.4 kHz sampling frequency.
PAUSE command input CS(I) MON(O) RPM Bit(O) VPM Bit(O) PAUSE command input
tPSCP
tSPCP1
AOUT(O) Status Playing Back Pausing Playing Back
PAUSE command input CS(I)
STOP command input tSPCM 165 s
MON(O) RPM Bit(O) VPM Bit(O) AOUT(O) tSPCR 165 s tPSCP tSPCP2 165 s
Status
Playing Back
Pausing
Command Wait
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FUNCTIONAL DESCRIPTION
Serial Peripheral Interface (SPI) ML2500B communicates with the external Micro-Controller Unit through the industry's standard Serial Peripheral Interface (SPI). 1. Timing for Writing Command Data The following charts show timings for writing command data. After "L" input to CS pin, input command data, starting with the MSB in serial order, to the DI pin in sync with the SCK signal. The command input to the DI pin is fetched to the LSI's internal shift resister at the rising edge of the SCK signal, and then the command is executed at the rising edge of the CS pin. The DI input is either of 4, 8, or 24th bit. When the CS pin is brought to "H" level except at 4/8/24th bit for the command, the command input then is disregarded. It is a recommendable practice to input command data at the falling edge of the CS pin while having the SCK pin at "L".
4-bit Command Format
CS(I) SCK(I) DI(I) C3 C2 C1 C0 C3 C2 C1 C0
8-bit Command Format
CS(I)
SCK(I) DI(I) C3 C2 C1 C0 D3 D2 D1 D0 C3 C2 C1
24-bit Command Format
CS(I) 1 SCK(I) DI(I) C3 C2 C1 C0 X X X X X X X A12 2 3 4 5 6 7 8 9 10 11 12
CS(I) 13 SCK(I) DI(I) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 15 16 17 18 19 20 21 22 23 24
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2. Timings for Reading out Status Data Status data that can be read includes two types, the status register (refer to the section 1.7, RDSTAT Command) and the memory address counter (refer to the section 1.6, RDADR Command). Timings for reading status data are shown in the charts below. After "L" input to the CS pin, input the RDSTAT command to read status data. While the CS pin being held "L", status data is output to the DO pin in serial sequence starting with the MSB, in synchronization with the 4th pulse SCK's falling edge following the command input. After reading status data, the DO pin returns to "Hi-Z" status regardless the number of SCK pulse, when the CS pin is brought to "H" level.
Status Data Read-Out Timing
CS(I)
SCK(I) DI(I) DO(O) Hi-Z C3 C2 C1 C0 03 02 01 00 Hi-Z
Memory Address Counter Read-Out Timing
CS(I) 1 SCK(I) DI(I) DO(O) Hi-Z C3 C2 C1 C0 A12 A11 A10 A9 2 3 4 5 6 7 8 9 10 11 12 13 14
CS(I) 15 SCK(I) DI(I) DO(O) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hi-Z 16 17 18 19 20 21 22 23 24
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Control Commands You can control Record/Playback operations by using 4-bit commands through the serial interface. 1. Control Commands-Recording The following section describes commands used to control recording: 1.1. REC Command (1XH) By using the first 4 bits of this command, you can initiate recording, starting at the specified Start Address and recording lasts up to the specified Stop Address. When the specified Stop Address is reached, recording automatically ends up. 4-bit data preceded is to define a sampling frequency, as shown in the table below. When the sampling frequency is not defined with this command, recording is made at the last defined sampling frequency. When reset and powered up, recording is made at 6.4 kHz (default) sampling frequency. (With the internal oscillator or the external clock at 8.192 MHz)
Data 0H 1H 2H Sampling Frequency 4.0 kHz 5.3 kHz 6.4 kHz (Default)
You can specify the Start and Stop Addresses for a recording session by using the STADR and SPADR commands. See 1.4 and 1.5 of this Data Sheet for further details on the STADR and SPADR commands. 1.2. STOP Command (3H) You can stop recording by using this command. The data following to this command is disregarded. 1.3. PAUSE Command (4H) You can suspend recording temporarily by using this command. The data following to this command is disregarded. To re-input the command resumes the suspended operation. If the STOP command is input while recording is suspended by the PAUSE command, the LSI shifts to Record Ending operation and then terminates recording.
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1.4. STADR Command (5H) You can specify the Start Address for recording with 13-bit data preceded by this command. You need to run the STADR command before you can use the REC command. Due to the design of memory array configuration, lower 4-bit of 13-bit Start Address defined is automatically set to "0H". For further details, refer to "Addressable Memory Space for Recording" section. When this command is not executed prior to the REC command input, recording starts at the last defined Start Address. After resetting or power-on, the Start Address is set to the memory's starting address as default. 1.5. SPADR command (6H) You can specify the Stop Address for recording with 13-bit data preceded by this command. You need to run the SPADR command before you can use the REC command. When this command is not executed prior to the REC command input, recording ends at the last defined Stop Address. After resetting or power-on, the Stop Address is set to the memory's last address as default. 1.6. RDADR Command (7H) By using this command you can read the address pointed by the current Memory Address Counter via serial interface. In sync with SCK signal following to the RDADR command, 13-bit Memory Address Counter's value, starting with the MSB, is output to the DO pin. The DO pin's output falls down to "L" level after 13th bit. Right after recording stops, use this command to read the Stop Address of the phrase that has just been recorded. This allows the external MCU to control addresses for recorded phrases. This command can be input during recording and record pausing. However, running the RDADR command after the STADR (SPADR) command input, lets the LSI output the address defined by the STADR (SPADR) command. 1.7. RDSTAT Command (8H) By using this command you can read out the values of the internal Status Register via serial interface. Reading the Status Register's values lets you know ML2500B's internal status as shown in the table below. In sync with SCK signal following to the RDSTAT command bits, 4-bit Status Register's data is output to the DO pin, starting with the MSB. The DO pin's output after 4th bit falls down to the GND level.
Read Bit 03 02 01 00 Name MON VPM RPM FULL Status Description Output "H" level while in record/playback operation, physical recording/playback time plus memory control time. This output is identical value to that of the MON pin. Output "H" level while recording/playback being suspended by the PAUSE command. Output "H" level while in record/playback operation, physical recording/playback time only without memory control time. Output "H" level simultaneously when the MON pin turns "L" level as recording/playback ends by reaching the last address of memory.
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2. Control Commands-Playback The following section describes commands used to control playback: 2.1. PLAY Command (2XH) By using the first 4 bits of this command, you can initiate playback, starting at the specified Start Address and playback lasts up to the specified Stop Address. When the specified Stop Address is reached, playback automatically stops. 4-bit data preceded is to define a sampling frequency, same as with the REC command. When the sampling frequency is not defined with this command, playback is made last defined sampling frequency. When reset and powered up, playback is made at 6.4 kHz (default) sampling frequency. You can specify the Start and Stop Addresses for a playback session by using the STADR and SPADR commands. See 2.4 and 2.5 for further details on the STADR and SPADR commands. When the Start Address and the Stop Address are not defined by STADR and SPADR commands, playback is taken place by using the Start and Stop Addresses defined for the last playback session. 2.2. STOP Command (3H) You can stop playback by using this command. The data following to this command is disregarded. 2.3. PAUSE Command (4H) You can temporarily suspend playback by using this command. The data following to this command is disregarded. Re-inputting this command resumes the suspended operation. If the STOP command is input while playback is suspended by the PAUSE command, the LSI stops playback. 2.4. STADR Command (5H) You can specify the Start Address for playback with 13-bit data preceded by this command. You need to run STADR command before you can use the PLAY command. When this command is not executed prior to the PLAY command input, playback starts at the last defined Start Address. After resetting or power-on, the Start Address is set to the memory's starting address as default. 2.5. SPADR Command (6H) You can specify the Stop Address for playback with 13-bit data preceded by this command. You need to run the SPADR command before you can use the PLAY command. When this command is not executed prior to the PLAY command input, playback ends at the last defined Stop Address. After resetting or power-on, the Stop Address is set to the memory's last address as default. 2.6. RDADR Command (7H) By using this command you can read the address pointed by the current Memory Address Counter via serial interface. In synchronization with SCK signal following to the RDADR command, 13-bit Memory Address Counter's value, starting with the MSB, is output to the DO pin. The DO pin's output falls down to "L" level after 13th bit. This command can be input during playback and playback pausing.
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3. The List of Control Commands
Data Command Name NOOP
Start recording either at default or last-defined sampling frequency. (Initial frequency: 6.4 kHz)
Command Function No Particular Function
12345
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0 0 0 0---------------- -- -- -- -- -- -- -- -- -- -- -- --
OKI Semiconductor
0 0 0 1---------------- -- -- -- -- -- -- -- -- -- -- -- -- Record at fsam 4.0 kHz with int. oscillator or ext. clock at 8.192 MHz. Record at fsam 5.3 kHz with int. oscillator or ext. clock at 8.192 MHz. REC Record at fsam 6.4 kHz with int. oscillator or ext. clock at 8.192 MHz. Record at fsam 5.3 kHz with ext. clock at 4.096 MHz. *Not supported for int. osc. Record at fsam 6.4 kHz with ext. clock at 4.096 MHz. *Not supported for int. osc. Record at fsam 4.0 kHz with ext. clock at 4.096 MHz. *Not supported for int. osc.
Start playback either at default or last-defined sampling frequency. (Initial frequency: 6.4 kHz)
0
0
0
0 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
0
0
1 -------- -- -- -- -- -- -- -- -- -- -- -- --
3. The list of Control Commands
0
0
1
0 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
1
0
0 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
1
0
1 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
1
1
1 -------- -- -- -- -- -- -- -- -- -- -- -- --
0 0 1 0---------------- -- -- -- -- -- -- -- -- -- -- -- --
0
0
0
0 -------- -- -- -- -- -- -- -- -- -- -- -- --
Playback at fsam 4.0 kHz with int. oscillator or ext. clock 8.192 MHz. Playback at fsam 5.3 kHz with int. oscillator or ext. clock 8.192 MHz. PLAY Playback at fsam 6.4 kHz with int. oscillator or ext. clock 8.192 MHz. Playback at fsam 5.3 kHz with ext. clock at 4.096 MHz. *Not supported for int. osc. Playback at fsam 6.4 kHz with ext. clock at 4.096 MHz. *Not supported for int. osc. Playback at fsam 4.0 kHz with ext. clock at 4.096 MHz. *Not supported for int. osc. STOP Stop Record/Playback
0
0
0
1 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
0
1
0 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
1
0
0 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
1
0
1 -------- -- -- -- -- -- -- -- -- -- -- -- --
0
1
1
1 -------- -- -- -- -- -- -- -- -- -- -- -- --
0 0 1 1---------------- -- -- -- -- -- -- -- -- -- -- -- --
0 1 0 0---------------- -- -- -- -- -- -- -- -- -- -- -- --
PAUSE Pause Record/Playback, or reset PAUSE STADR Define Start Address for Record/Playback SPADR Define Stop Address for Record/Playback RDADR Read out Memory Address Counter value RDSTAT Read out Status Register data PDWN Power-down to enter into power saving mode
0 1 0 1 X X X X X X X A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 1 0 X X X X X X X A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 1 1 X X X X X X X A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 ----------------
1 0 0 0 X X X X O3 O2 O1 O0 0
0
1 0 0 1---------------- -- -- -- -- -- -- -- -- -- -- -- --
FEDL2500BFULL-02
ML2500BTA
Note: The device is guaranteed for operation for the values included in the list above, so values other than those in the list should not be input.
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
Addressable Memory Space for Recording The total memory space of the ML2500B is divided into 4 blocks, 256 K bit-cell for each block, and a block is divided into 80 sectors, 3.2 K bit-cell for each sector. Finally, a sector is divided into 16 pages, 200 bit-cell for each page. A12 to A11 are assigned to represent a block address, A10 to A4 to represent a sector address, and A3 to A0 to represent a page address.
TOTAL MEMORY SPACE 1M Bit-Cell Block Address (A12 to A11) 0H 1H 2H 3H
A BLOCK SPACE 256K Bit-Cell Sector Address (A10 to A4)
00H 01H 02H 03H A SECTOR SPACE 3.2K Bit-Cell
4CH 4DH 4EH 4FH
Page Address (A3 to A0)
0H
1H
2H
3H
CH
DH
EH
FH
A PAGE SPACE 200 Bit-Cell
Address Assignment to Define Block, Sector and Page Address for Start and Stop Address
A12 A11 A10 Block Address A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Sector Address
Page Address
Prohibit specified addresses for Start Address and Stop Address These below addresses are prohibited when Start Address or Stop Address is specified. 0500H07FFH 0D00H0FFFH 1500H17FFH 1D00H1FFFH
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
Example for setting address The below table shows the example for Start Address and Stop Address when the memory which is divided into 8 phrases is recorded and played.
Start Address Phrase No. Block A12,A11 0 0 1 1 2 2 3 3 Sector A10 A4 00 28 00 28 00 28 00 28 Page A3 A0 0 0 0 0 0 0 0 0 Specified Address A12 A0 0000 0280 0800 0A80 1000 1280 1800 1A80 Stop Address Block A12,A11 0 0 1 1 2 2 3 3 Sector A10 A4 27 4F 27 4F 27 4F 27 4F Page A3 A0 F F F F F F F F Specified Address A12 A0 027F 04FF 0A7F 0CFF 127F 14FF 1A7F 1CFF
[0H 3H] [00H 4FH] [0H FH] CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
[0H 3H] [00H 4FH] [0H FH]
Address Control 1. Address Control for Recording The LSI is designed to make recording in sectors, as the minimum recording unit. When a user sets up the Starting Address for recording by using the STADR command, the page address, lower 4-bit of 13-bit user-defined Starting Address, is automatically set to "0H" internally. Thus recording always begins at the starting address of each sectors. Meanwhile, when you define the Stop Address for recording by using the SPADR command, full 13-bit address definition is valid. This enables you to specify the Stop Address for recording in pages. However, within the LSI recording continues as far as to the last address of the following sector. If the RDADR command is used to read the address value of the Memory Address Counter after completion of recording, output value represents the Memory Address Counter's value either at the time when the Stop Address defined by the SPADR command has been reached, or when the LSI receives the STOP command that causes the LSI to stop recording. 2. Address Control for Playback The LSI is designed to make playback in pages, as the minimum playback unit, so full 13-bit address definition is valid both with the STADR command and the SPADR command. You can, therefore, specify the start and stop location by unit of page.
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
LPF Characteristics The LSI has an on-chip 4-stage LPF which utilizes Switched Capacitor Filtering technology. Attenuation is set to -40dB/oct. while the cut-off frequency and frequency characteristics vary in proportion to the sampling frequency (fs) selected. The cut-off frequency is set to 0.4 level of the selected sampling frequency. Power Supply Circuit Design As shown in the following figure, power supply to the LSI must be designed to have a single power source, and separate wiring for analog section and logic section.
+3 V
DVDD
AVDD
ML2500BTA
DGND
AGND
The following figures are bad wiring samples you should avoid.
Analog Power Supply Digital Power Supply
Power Supply
DVDD
AVDD
DVDD
AVDD
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
LOUT Output Voltage Range Allowance
Voice Waveform 2.2 V 0.5 V R1 R2 LIN Pin - + SG (Signal GND) 1.35 V LOUT Pin Beep 0.5 V SG Voltage 0.5 V LOUT Output Signal (VLOUT)
Connect to LPF
The LSI has a built-in OP amplifier to amplify incoming analog source signal. The inverting input pin to the OP amplifier (LIN pin) and the output pin from the OP amplifier (LOUT pin) are available. The non-inverting input is internally connected to the Reference Voltage (Signal Ground 1.35 V). As shown in the above wiring sample, the ML2500B is configured so that recording signal can be created through inverting amplifying circuit configured by connecting external resistors, R1 and R2, to the LIN pin and the LOUT pin. The LOUT pin's output voltage (VLOUT) becomes actual recording voltage, and thus is input to the LPF within the LSI. It is recommended to adjust the amplifying rate so that the dynamic range of the VLOUT voltage will be from 0.5 to 2.2 V for voice input and will be 0.5 V with respect to the SG voltage for beep. If the VLOUT voltage exceeds the recommended voltage range, then the LSI's internal LPF's output would be clipped waveform, resulting in degradation of memory reliability. States of Output Pins during Power Down
Pins AOUT DO MON SG States of output pins during power down GND level High impedance (Hi-Z) "L" level GND level
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
APPLICATION CIRCUITS
Power Supply (+3 V) 0.1 F 0.1 F
DVDD
AV DD
RESET CS MCU DI DO SCK AOUT MSC1157
LOUT 51 pF 200 k
0.47 F LIN LINE IN 30 k TEST1 EXCLK
ROSC
DGND 30 k
ML2500BTA
SG AGND 3300 pF
MON
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
PACKAGE DIMENSIONS
(Unit: mm)
TSOP(1)32-P-0814-0.50-1K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.27 TYP. 3/Dec. 10, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
REVISION HISTORY
Page Document No. FEDL2500BFULL-01 Date Nov, 2000 Previous Edition 14 Current Edition 14 Final edition 1 Corrected the chart of 8bit command and format. Added mentioned about prohibiting specified addresses for Start Address and Stop Address. Added the Example for setting address. Description
FEDL2500BFULL-02
Aug. 9, 2004
20
21
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FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
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